职称：

副教授、硕士生导师

 

电子邮箱：

xiaoshlin@mail.sysu.edu.cn

 

学术经历：

中山大学            微电子科学与技术学院    副教授

中山大学            电子与信息工程学院      副研究员

日本东京工业大学    通信与计算机工学        博士

日本东京工业大学    通信与计算机工学        Research Student

电子科技大学        通信与信息系统          硕士

电子科技大学        通信工程                学士

 

授课课程：

  • 《微机原理与嵌入式系统》(本科)
  • 《微机原理与嵌入式系统实验》(本科)
  • 《超大规模数字集成电路设计》(研究生)
  • 《微处理器体系架构与设计》(研究生)

 

研究方向：

数字集成电路设计、计算机体系结构

  1. 芯片：类脑芯片、人工智能芯片
  2. 架构：领域专用架构、可重构计算架构
  3. 方法学：异步电路设计方法、机器学习算法/硬件协同设计方法

 

科研项目：

  1. 国家自然科学基金重点项目，片上自学习全异步类脑计算芯片关键技术研究，2024/01-2028/12，主要参与人
  2. 广东省重点领域研发计划，大规模在线学习类脑芯片架构及应用，2023/06-2026/06，子课题负责人
  3. 国家自然科学基金青年科学基金项目，数据驱动异步专用处理器能效问题研究，2020/01-2022/12，负责人
  4. 国家重点研发计划课题，多颗粒度可重构计算架构研究，2019/08-2022/07，子课题负责人
  5. 国家自然科学基金重点项目，可编程动态自重构三维阵列芯片体系结构关键技术，2019/01-2023/12，主要参与人
  6. 多项华为公司横向项目，负责人

 

学术兼职和社会服务：

  1. 学术会议技术委员会成员
  • IEEE International Conference on Integrated Circuits, Technologies and Applications, TPC Member, 2020年至今
  1. 学术期刊审稿人
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems
  • IEEE Transactions on Circuits and Systems I: Regular Papers
  • IEEE Transactions on Circuits and Systems II: Express Briefs
  • IEEE Transactions on Biomedical Circuits and Systems
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems

 

代表性科研成果：

  1. Wei Liu, Shanlin Xiao*, Yue Liu and Zhiyi Yu*, "SC-PLR: An Approximate Spiking Neural Network Accelerator with On-Chip Predictive Learning Rule," in IEEE Transactions on Biomedical Circuits and Systems, 2024.
  2. Lingfeng Zhou, Shanlin Xiao*, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu, "Better-Than-Worst-Case: A Frequency Adaptation Asynchronous RISC-V Core With Vector Extension," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2024.
  3. Huiyao Wang, Shanlin Xiao*, Lingfeng Zhou, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu*, "LAC: A Novel Lightweight Asynchronous Controller with Optimized Phase Shift," in IEEE Transactions on Circuits and Systems II: Express Briefs, 2024.
  4. Yuhao Huang, Shanlin Xiao*, Zhiyu Li and Zhiyi Yu*, "An Asynchronous Bundled-Data Template With Current Sensing Completion Detection Technique," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 9, pp. 3904-3908, Sept. 2022.
  5. Zhiyu Li, Yuhao Huang, Longfeng Tian, Ruimin Zhu, Shanlin Xiao* and Zhiyi Yu*, "A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 9, pp. 3153-3157, Sept. 2021.
  6. Huanliang Zheng, Yuhao Guo, Xingyu Yang, Shanlin Xiao* and Zhiyi Yu*, "Balancing the Cost and Performance Trade-Offs in SNN Processors," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 9, pp. 3172-3176, Sept. 2021.
  7. Shanlin Xiao, Weikun Liu, Junshu Lin, Zhiyi Yu*, "A Data-Driven Asynchronous Neural Network Accelerator," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 9, pp. 1874-1886, Sept. 2021.
  8. Mingyuan Meng, Xingyu Yang, Lei Bi, Jinman Kim, Shanlin Xiao* and Zhiyi Yu*, "High-parallelism Inception-like Spiking Neural Networks for Unsupervised Feature Learning," Neurocomputing 441: 92-104 (2021).
  9. Shanlin Xiao#, Wei Liu#, Yuhao Guo, Zhiyi Yu*, "Low-Cost Adaptive Exponential Integrate-and-Fire Neuron Using Stochastic Computing," in IEEE Transactions on Biomedical Circuits and Systems, vol. 14, no. 5, pp. 942-950, Oct. 2020.
  10. Shanlin Xiao, Yuhao Guo, Wenkang Liao, Huipeng Deng, Yi Luo, Huanliang Zheng, Jian Wang, Cheng Li, Gezi Li, Zhiyi Yu*, "NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 9, pp. 1966-1978, Sept. 2020.
  11. Shanlin Xiao, Tsuyoshi Isshiki*, Dongju Li, Hiroaki Kunieda, "HOG-Based Object Detection Processor Design Using ASIP Methodology," IEICE Transactions on Fundamentals, 2017, E100-A(12): 2972~2984.
  12. Shanlin Xiao, Tsuyoshi Isshiki*, Dongju Li, Hiroaki Kunieda, "Design of an Application Specific Instruction Set Processor for Real-Time Object Detection Using AdaBoost Algorithm," IEICE Transactions on Fundamentals, 2017, E100-A(07): 1384~1395.
  13. Lingfeng Zhou, Shanlin Xiao*, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang, Zhiyi Yu, "An Efficient Asynchronous Circuits Design Flow with Backward Delay Propagation Constraint," 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia, Spain, 2024, pp. 1-6.
  14. Yue Liu, Shanlin Xiao*, Bo Li and Zhiyi Yu*, "Sparsespikformer: A Co-Design Framework for Token and Weight Pruning in Spiking Transformer," 2024 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Seoul, Korea, Republic of, 2024, pp. 6410-6414.
  15. Hui Deng, Jian Wang, Huafeng Ye, Shanlin Xiao*, Xiangyu Meng and Zhiyi Yu*, "3D-VNPU: A Flexible Accelerator for 2D/3D CNNs on FPGA," 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Orlando, USA, 2021, pp. 181-185.
  16. Xingyu Yang, Mingyuan Meng, Shanlin Xiao* and Zhiyi Yu*, "SPA: Stochastic Probability Adjustment for System Balance of Unsupervised SNNs," 2020 25th International Conference on Pattern Recognition (ICPR), Milan, Italy, 2021, pp. 6417-6424.
  17. Mingyuan Meng, Xingyu Yang, Shanlin Xiao*, Zhiyi Yu*, "Spiking Inception Module for Multi-layer Unsupervised Spiking Neural Networks," 2020 International Joint Conference on Neural Networks (IJCNN), Glasgow, UK, 2020, pp. 1-8.
  18. Shanlin Xiao, Tsuyoshi Isshiki*, Dongju Li, Hiroaki Kunieda, "An Efficient Embedded Processor for Object Detection Using ASIP Methodology," 2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP), London, UK, 2016, pp. 225-226.

(*通讯作者、#共同第一作者)