职称：
副教授、博士生导师
电子邮箱：
xiaoshlin@mail.sysu.edu.cn
学术经历：
中山大学 微电子科学与技术学院 副教授
中山大学 电子与信息工程学院 副研究员
日本东京工业大学 通信与计算机工学 博士
日本东京工业大学 通信与计算机工学 Research Student
电子科技大学 通信与信息系统 硕士
电子科技大学 通信工程 学士
授课课程：
《微机原理》(本科)
《微机原理实验》(本科)
《微处理器体系架构与设计》(本科、研究生)
《数字集成电路设计与实践》(研究生)
研究方向：
数字集成电路设计、类脑芯片、新型计算架构、人工智能算法/硬件协同设计
科研项目：
（1）国家自然科学基金重点项目，片上自学习全异步类脑计算芯片关键技术研究，2024/01-2028/12，主要参与人
（2）广东省重点领域研发计划，大规模在线学习类脑芯片架构及应用，2023/06-2026/06，子课题负责人
（3）国家自然科学基金青年科学基金项目，数据驱动异步专用处理器能效问题研究，2020/01-2022/12，负责人
（4）国家重点研发计划课题，多颗粒度可重构计算架构研究，2019/08-2022/07，子课题负责人
（5）国家自然科学基金重点项目，可编程动态自重构三维阵列芯片体系结构关键技术，2019/01-2023/12，主要参与人
（6）多项华为公司横向项目，负责人
学术兼职和社会服务：
学术会议技术委员会成员
IEEE International Conference on Integrated Circuits, Technologies and Applications, TPC Member, 2020年至今
学术期刊审稿人
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems
IEEE Transactions on Circuits and Systems I: Regular Papers
IEEE Transactions on Circuits and Systems II: Express Briefs
IEEE Transactions on Biomedical Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Emerging Topics in Computational Intelligence
近年代表性科研成果：(*通讯作者、#共同第一作者)
(1) 期刊论文
[1] Jinghai Wang, Jilong Luo, Bo Li, Lingfeng Zhou, Zhiyi Yu and Shanlin Xiao*, "ASNA-Flow: An Efficient Asynchronous Neuromorphic Accelerator for Real-Time Event-Based Optical Flow," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2025.
[2] Wei Liu, Yue Liu, Zhiyi Yu and Shanlin Xiao*, "A Hybrid Stochastic-Binary Computing Batch Normalization Engine for Low-Power On-Chip Learning Spiking Neural Networks," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2025.
[3] Jinghai Wang, Shanlin Xiao*, Jilong Luo, Bo Li, Lingfeng Zhou and Zhiyi Yu, "An End-to-End Bundled-Data Asynchronous Circuits Design Flow: From RTL to GDS," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 33, no. 1, pp. 154-167, Jan. 2025.
[4] Wei Liu, Shanlin Xiao*, Yue Liu and Zhiyi Yu*, "SC-PLR: An Approximate Spiking Neural Network Accelerator with On-Chip Predictive Learning Rule," in IEEE Transactions on Biomedical Circuits and Systems, vol. 18, no. 5, pp. 1156-1165, Oct. 2024.
[5] Lingfeng Zhou, Shanlin Xiao*, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang and Zhiyi Yu*, "Toward Efficient Asynchronous Circuits Design Flow Using Backward Delay Propagation Constraint," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 32, no. 10, pp. 1852-1863, Oct. 2024.
[6] Lingfeng Zhou, Shanlin Xiao*, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang and Zhiyi Yu, "Better-Than-Worst-Case: A Frequency Adaptation Asynchronous RISC-V Core With Vector Extension," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 32, no. 6, pp. 1045-1057, June 2024.
[7] Huiyao Wang, Shanlin Xiao*, Lingfeng Zhou, Jinghai Wang, Zeyang Xu, Bohan Wang and Zhiyi Yu*, "LAC: A Novel Lightweight Asynchronous Controller with Optimized Phase Shift," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 8, pp. 3920-3924, Aug. 2024.
[8] Yuhao Huang, Shanlin Xiao*, Zhiyu Li and Zhiyi Yu*, "An Asynchronous Bundled-Data Template With Current Sensing Completion Detection Technique," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 9, pp. 3904-3908, Sept. 2022.
[9] Zhiyu Li, Yuhao Huang, Longfeng Tian, Ruimin Zhu, Shanlin Xiao* and Zhiyi Yu*, "A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 9, pp. 3153-3157, Sept. 2021.
[10] Huanliang Zheng, Yuhao Guo, Xingyu Yang, Shanlin Xiao* and Zhiyi Yu*, "Balancing the Cost and Performance Trade-Offs in SNN Processors," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 9, pp. 3172-3176, Sept. 2021.
[11] Shanlin Xiao, Weikun Liu, Junshu Lin and Zhiyi Yu*, "A Data-Driven Asynchronous Neural Network Accelerator," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 9, pp. 1874-1886, Sept. 2021.
[12] Mingyuan Meng, Xingyu Yang, Lei Bi, Jinman Kim, Shanlin Xiao* and Zhiyi Yu*, "High-parallelism Inception-like Spiking Neural Networks for Unsupervised Feature Learning," Neurocomputing 441: 92-104 (2021).
[13] Shanlin Xiao#, Wei Liu#, Yuhao Guo and Zhiyi Yu*, "Low-Cost Adaptive Exponential Integrate-and-Fire Neuron Using Stochastic Computing," in IEEE Transactions on Biomedical Circuits and Systems, vol. 14, no. 5, pp. 942-950, Oct. 2020.
[14] Shanlin Xiao, Yuhao Guo, Wenkang Liao, Huipeng Deng, Yi Luo, Huanliang Zheng, Jian Wang, Cheng Li, Gezi Li and Zhiyi Yu*, "NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 9, pp. 1966-1978, Sept. 2020. Conference (ASP-DAC), Hong Kong, China, 2026, pp. 1–7.
(2) 会议论文
[1] Wei Liu, Yinsheng Chen, Jilong Luo, Yusa Wang, Zhiyi Yu and Shanlin Xiao*, "An Algorithm-Hardware Co-Design for Efficient and Robust Spiking Neural Networks via Sparsity," 2026 31th Asia and South Pacific Design Automation
[2] Jianzhen Gao, Wei Liu, Yue Liu, Hengyi Zhou, Zhiyi Yu and Shanlin Xiao*, "Spiking-NeRF: Neural Graphics Acceleration With Spiking Feature Encoding for Edge 3D Rendering," 2026 31th Asia and South Pacific Design Automation Conference (ASP-DAC), Hong Kong, China, 2026, pp. 1–7.
[3] Wei Liu, Yue Liu, Bo Li, Ningyuan Yin, Jilong Luo, Yinsheng Chen, Zhiyi Yu and Shanlin Xiao*, "BIONIC: A 64-Core SNN/RISC-V Reconfigurable Processor with Hybrid On-Chip Learning Achieving 0.62 pJ/SOP and >99% Core Utilization," 2025 IEEE Asian Solid-State Circuits Conference (A-SSCC), Daejeon, Korea, Republic of, 2025, pp. 1-3.
[4] Yihe Yu#, Bo Li#, Kexin Huang, Wei Liu, Jinghai Wang, Yue Liu, Zhiyi Yu and Shanlin Xiao* "Towards In-Situ Neuromorphic Computing Architecture for Event Stream Super-Resolution," 2025 62nd ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 2025, pp. 1-7.
[5] Bo Li, Yue Liu, Wei Liu, Jinghai Wang, Xiao Huang, Zhiyi Yu and Shanlin Xiao*, "SCSC: Leveraging Sparsity and Fault-Tolerance for Energy-Efficient Spiking Neural Networks," 2025 30th Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, 2025, pp. 741–747.
[6] Bohan Wang, Zeyang Xu, Lingfeng Zhou, Huiyao Wang, Jinghai Wang, Zhiyi Yu and Shanlin Xiao*, "A Time-Borrowing Method for High-Performance Bundled-Data Asynchronous Circuits," 2025 26th International Symposium on Quality Electronic Design (ISQED), San Francisco, CA, USA, 2025, pp. 1-6.
[7] Lingfeng Zhou, Shanlin Xiao*, Huiyao Wang, Jinghai Wang, Zeyang Xu, Bohan Wang and Zhiyi Yu, "An Efficient Asynchronous Circuits Design Flow with Backward Delay Propagation Constraint," 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), Valencia, Spain, 2024, pp. 1-6.
[8] Yue Liu, Shanlin Xiao*, Bo Li and Zhiyi Yu*, "Sparsespikformer: A Co-Design Framework for Token and Weight Pruning in Spiking Transformer," 2024 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Seoul, Korea, Republic of, 2024, pp. 6410-6414.
[9] Hui Deng, Jian Wang, Huafeng Ye, Shanlin Xiao*, Xiangyu Meng and Zhiyi Yu*, "3D-VNPU: A Flexible Accelerator for 2D/3D CNNs on FPGA," 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Orlando, USA, 2021, pp. 181-185.
